用于CMOS图像传感器的低功耗增量Delta-sigma自适应偏置ADC

IF 0.5 4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Journal of Semiconductor Technology and Science Pub Date : 2023-10-31 DOI:10.5573/jsts.2023.23.5.314

Dong-Hwan Seo, Jung-Gyun Kim, Byung-Geun Lee

{"title":"用于CMOS图像传感器的低功耗增量Delta-sigma自适应偏置ADC","authors":"Dong-Hwan Seo, Jung-Gyun Kim, Byung-Geun Lee","doi":"10.5573/jsts.2023.23.5.314","DOIUrl":null,"url":null,"abstract":"This paper presents the design and fabrication of a low-power incremental delta-sigma analog-to-digital converter (ADC) with an adaptive bias technique suitable for complimentary metaloxide semiconductor (CMOS) image sensors (CISs). The adaptive biasing circuitry provides the amplifier with a predicted minimum current value required for the integrator output to settle; this optimized current flows through the amplifier and reduces power consumption by 40%. A prototype ADC fabricated using a 0.18 μm CMOS process, achieves an SNDR of 65 dB at a sampling frequency of 25 MHz and consumes 13.5 μW from a 1.8 V power supply. The measured differential and integral nonlinearities are +0.31/-0.42 and +0.62/-0.75 at a 12-bit accuracy, respectively.","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":null,"pages":null},"PeriodicalIF":0.5000,"publicationDate":"2023-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Low-power Incremental Delta-sigma ADC with Adaptive Biasing for CMOS Image Sensors\",\"authors\":\"Dong-Hwan Seo, Jung-Gyun Kim, Byung-Geun Lee\",\"doi\":\"10.5573/jsts.2023.23.5.314\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design and fabrication of a low-power incremental delta-sigma analog-to-digital converter (ADC) with an adaptive bias technique suitable for complimentary metaloxide semiconductor (CMOS) image sensors (CISs). The adaptive biasing circuitry provides the amplifier with a predicted minimum current value required for the integrator output to settle; this optimized current flows through the amplifier and reduces power consumption by 40%. A prototype ADC fabricated using a 0.18 μm CMOS process, achieves an SNDR of 65 dB at a sampling frequency of 25 MHz and consumes 13.5 μW from a 1.8 V power supply. The measured differential and integral nonlinearities are +0.31/-0.42 and +0.62/-0.75 at a 12-bit accuracy, respectively.\",\"PeriodicalId\":17067,\"journal\":{\"name\":\"Journal of Semiconductor Technology and Science\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.5000,\"publicationDate\":\"2023-10-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Journal of Semiconductor Technology and Science\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.5573/jsts.2023.23.5.314\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Semiconductor Technology and Science","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.5573/jsts.2023.23.5.314","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

摘要

本文介绍了一种适用于互补金属氧化物半导体(CMOS)图像传感器(CISs)的低功耗增量delta-sigma模数转换器(ADC)的设计和制造。自适应偏置电路为放大器提供积分器输出所需的预测最小电流值;经过优化的电流流经放大器，降低了40%的功耗。采用0.18 μm CMOS工艺制作的原型ADC在采样频率为25 MHz时SNDR为65 dB，功耗为13.5 μW，电源电压为1.8 V。在12位精度下，测量到的微分和积分非线性分别为+0.31/-0.42和+0.62/-0.75。

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A Low-power Incremental Delta-sigma ADC with Adaptive Biasing for CMOS Image Sensors

This paper presents the design and fabrication of a low-power incremental delta-sigma analog-to-digital converter (ADC) with an adaptive bias technique suitable for complimentary metaloxide semiconductor (CMOS) image sensors (CISs). The adaptive biasing circuitry provides the amplifier with a predicted minimum current value required for the integrator output to settle; this optimized current flows through the amplifier and reduces power consumption by 40%. A prototype ADC fabricated using a 0.18 μm CMOS process, achieves an SNDR of 65 dB at a sampling frequency of 25 MHz and consumes 13.5 μW from a 1.8 V power supply. The measured differential and integral nonlinearities are +0.31/-0.42 and +0.62/-0.75 at a 12-bit accuracy, respectively.

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来源期刊

Journal of Semiconductor Technology and Science ENGINEERING, ELECTRICAL & ELECTRONIC-PHYSICS, APPLIED

CiteScore

0.90

自引率

0.00%

发文量

审稿时长

6-12 weeks

期刊介绍： Journal of Semiconductor Technology and Science is published to provide a forum for R&D people involved in every aspect of the integrated circuit technology, i.e., VLSI fabrication process technology, VLSI device technology, VLSI circuit design and other novel applications of this mass production technology. When IC was invented, these people worked together in one place. However, as the field of IC expanded, our individual knowledge became narrower, creating different branches in the technical society, which has made it more difficult to communicate as a whole. The fisherman, however, always knows that he can capture more fish at the border where warm and cold-water meet. Thus, we decided to go backwards gathering people involved in all VLSI technology in one place.