基于时基LSB解码器的20 gb /s双模阈值电压自适应PAM-4接收机

IF 0.5 4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Journal of Semiconductor Technology and Science Pub Date : 2023-10-31 DOI:10.5573/jsts.2023.23.5.303

Jeong-Mi Park, Jin-Ku Kang

{"title":"基于时基LSB解码器的20 gb /s双模阈值电压自适应PAM-4接收机","authors":"Jeong-Mi Park, Jin-Ku Kang","doi":"10.5573/jsts.2023.23.5.303","DOIUrl":null,"url":null,"abstract":"This paper presents a pulse amplitude modulation-4 (PAM-4) receiver with dual-mode threshold voltage applied to a time-based LSB decoder. The proposed receiver can select the threshold voltage that improves the robustness to sampler voltage variations. It also presents a random data-based threshold voltage adaptation using a single error sampler. Compared to the conventional PAM-4 threshold voltage adaptation that finds four data levels, this method finds only two levels, which reduces the overall power consumption, hardware complexity and adaptation time. The 20-Gb/s PAM-4 serial link was designed in a 65 nm CMOS Technology and analyzed with XMODEL and Cadence Design System","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":null,"pages":null},"PeriodicalIF":0.5000,"publicationDate":"2023-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 20-Gb/s PAM-4 Receiver with Dual-mode Threshold Voltage Adaptation using a Time-based LSB Decoder\",\"authors\":\"Jeong-Mi Park, Jin-Ku Kang\",\"doi\":\"10.5573/jsts.2023.23.5.303\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a pulse amplitude modulation-4 (PAM-4) receiver with dual-mode threshold voltage applied to a time-based LSB decoder. The proposed receiver can select the threshold voltage that improves the robustness to sampler voltage variations. It also presents a random data-based threshold voltage adaptation using a single error sampler. Compared to the conventional PAM-4 threshold voltage adaptation that finds four data levels, this method finds only two levels, which reduces the overall power consumption, hardware complexity and adaptation time. The 20-Gb/s PAM-4 serial link was designed in a 65 nm CMOS Technology and analyzed with XMODEL and Cadence Design System\",\"PeriodicalId\":17067,\"journal\":{\"name\":\"Journal of Semiconductor Technology and Science\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.5000,\"publicationDate\":\"2023-10-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Journal of Semiconductor Technology and Science\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.5573/jsts.2023.23.5.303\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Semiconductor Technology and Science","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.5573/jsts.2023.23.5.303","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

摘要

本文提出了一种脉冲幅度调制-4 (PAM-4)接收机，其双模阈值电压应用于基于时间的LSB解码器。该接收机可以选择阈值电压，提高对采样器电压变化的鲁棒性。提出了一种基于随机数据的阈值电压自适应方法。与传统PAM-4阈值电压自适应需要查找4个数据电平相比，该方法只查找2个电平，降低了总体功耗、硬件复杂度和自适应时间。采用65 nm CMOS工艺设计了20 gb /s PAM-4串行链路，并利用XMODEL和Cadence Design System进行了分析

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A 20-Gb/s PAM-4 Receiver with Dual-mode Threshold Voltage Adaptation using a Time-based LSB Decoder

This paper presents a pulse amplitude modulation-4 (PAM-4) receiver with dual-mode threshold voltage applied to a time-based LSB decoder. The proposed receiver can select the threshold voltage that improves the robustness to sampler voltage variations. It also presents a random data-based threshold voltage adaptation using a single error sampler. Compared to the conventional PAM-4 threshold voltage adaptation that finds four data levels, this method finds only two levels, which reduces the overall power consumption, hardware complexity and adaptation time. The 20-Gb/s PAM-4 serial link was designed in a 65 nm CMOS Technology and analyzed with XMODEL and Cadence Design System

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Journal of Semiconductor Technology and Science ENGINEERING, ELECTRICAL & ELECTRONIC-PHYSICS, APPLIED

CiteScore

0.90

自引率

0.00%

发文量

审稿时长

6-12 weeks

期刊介绍： Journal of Semiconductor Technology and Science is published to provide a forum for R&D people involved in every aspect of the integrated circuit technology, i.e., VLSI fabrication process technology, VLSI device technology, VLSI circuit design and other novel applications of this mass production technology. When IC was invented, these people worked together in one place. However, as the field of IC expanded, our individual knowledge became narrower, creating different branches in the technical society, which has made it more difficult to communicate as a whole. The fisherman, however, always knows that he can capture more fish at the border where warm and cold-water meet. Thus, we decided to go backwards gathering people involved in all VLSI technology in one place.