深度学习分割建模的SiN, SiO<SUB>2</SUB>高带宽存储器薄膜沉积工艺缺陷

IF 0.5 4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Journal of Semiconductor Technology and Science Pub Date : 2023-10-31 DOI:10.5573/jsts.2023.23.5.251

Intae Whoang, Chinkwan Cho, Jin-Hee Hong, Dong-Hee Son, Byung-Yoon Lim, Jin-Pyung Kim, Kijun Bang

引用次数: 0

摘要

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Deep Learning Segmentation Modeling for SiN, SiO<SUB>2</SUB> Film Deposition Process Defect of High Bandwidth Memory

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来源期刊

Journal of Semiconductor Technology and Science ENGINEERING, ELECTRICAL & ELECTRONIC-PHYSICS, APPLIED

CiteScore

0.90

自引率

0.00%

发文量

审稿时长

6-12 weeks

期刊介绍： Journal of Semiconductor Technology and Science is published to provide a forum for R&D people involved in every aspect of the integrated circuit technology, i.e., VLSI fabrication process technology, VLSI device technology, VLSI circuit design and other novel applications of this mass production technology. When IC was invented, these people worked together in one place. However, as the field of IC expanded, our individual knowledge became narrower, creating different branches in the technical society, which has made it more difficult to communicate as a whole. The fisherman, however, always knows that he can capture more fish at the border where warm and cold-water meet. Thus, we decided to go backwards gathering people involved in all VLSI technology in one place.