97.7 db DR 12.3 μ w 1 khz带宽2<SUP> and </SUP>阶Delta-sigma调制器,带全差分ab类运算放大器,采用浮动ab类控制

IF 0.5 4区 工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC
Byeong-Ho Yu, Jun-Ho Boo, Jae-Geun Lim, Hyoung-Jung Kim, Jae-Hyuk Lee, Gil-Cho Ahn
{"title":"97.7 db DR 12.3 μ w 1 khz带宽2&lt;SUP&gt; and &lt;/SUP&gt;阶Delta-sigma调制器,带全差分ab类运算放大器,采用浮动ab类控制","authors":"Byeong-Ho Yu, Jun-Ho Boo, Jae-Geun Lim, Hyoung-Jung Kim, Jae-Hyuk Lee, Gil-Cho Ahn","doi":"10.5573/jsts.2023.23.5.265","DOIUrl":null,"url":null,"abstract":"This paper presents a 2SUPnd/SUP order modified feed-forward (FF) delta-sigma modulator. To reduce power consumption, the proposed analog-to-digital converter (ADC) adopts a class-AB op-amp for the first integrator since it shows an enhanced slew rate with low quiescent current. In addition, a 4-bit asynchronous successive approximation register (SAR) ADC which exhibits low power consumption is employed as a quantizer. A delay is incorporated into the feedback path for stable operation of the feedback loop. The prototype ADC is fabricated in a 28 nm CMOS process, and the core area is 0.095 mm2. It consumes 12.3 μW from 0.8 V (Analog)/0.85 V (Digital) supply voltages at an operating clock frequency of 512 kHz with an oversampling ratio (OSR) of 256. It achieves a dynamic range (DR) of 97.7 dB and a peak signal-to-noise and distortion ratio (SNDR) of 94.8 dB, corresponding to a Schreier figure-of-merit (FoM) of 176.8 dB.","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":"43 4 1","pages":"0"},"PeriodicalIF":0.5000,"publicationDate":"2023-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 97.7-dB DR 12.3-μW 1-kHz Bandwidth 2&lt;SUP&gt;nd&lt;/SUP&gt; Order Delta-sigma Modulator with a Fully Differential Class-AB Op-Amp using Floating Class-AB Control\",\"authors\":\"Byeong-Ho Yu, Jun-Ho Boo, Jae-Geun Lim, Hyoung-Jung Kim, Jae-Hyuk Lee, Gil-Cho Ahn\",\"doi\":\"10.5573/jsts.2023.23.5.265\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 2SUPnd/SUP order modified feed-forward (FF) delta-sigma modulator. To reduce power consumption, the proposed analog-to-digital converter (ADC) adopts a class-AB op-amp for the first integrator since it shows an enhanced slew rate with low quiescent current. In addition, a 4-bit asynchronous successive approximation register (SAR) ADC which exhibits low power consumption is employed as a quantizer. A delay is incorporated into the feedback path for stable operation of the feedback loop. The prototype ADC is fabricated in a 28 nm CMOS process, and the core area is 0.095 mm2. It consumes 12.3 μW from 0.8 V (Analog)/0.85 V (Digital) supply voltages at an operating clock frequency of 512 kHz with an oversampling ratio (OSR) of 256. It achieves a dynamic range (DR) of 97.7 dB and a peak signal-to-noise and distortion ratio (SNDR) of 94.8 dB, corresponding to a Schreier figure-of-merit (FoM) of 176.8 dB.\",\"PeriodicalId\":17067,\"journal\":{\"name\":\"Journal of Semiconductor Technology and Science\",\"volume\":\"43 4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.5000,\"publicationDate\":\"2023-10-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Journal of Semiconductor Technology and Science\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.5573/jsts.2023.23.5.265\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Semiconductor Technology and Science","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.5573/jsts.2023.23.5.265","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

摘要

提出了一种2supd /SUP阶数修正前馈(FF) delta-sigma调制器。为了降低功耗,所提出的模数转换器(ADC)采用ab类运放作为第一积分器,因为它具有低静态电流的增强摆率。此外,采用低功耗的4位异步连续逼近寄存器(SAR) ADC作为量化器。为了保证反馈回路的稳定运行,在反馈路径中加入了延迟。原型ADC采用28 nm CMOS工艺制作,核心面积为0.095 mm2。在工作时钟频率为512 kHz时,0.8 V(模拟)/0.85 V(数字)电源电压消耗12.3 μW,过采样比(OSR)为256。它的动态范围(DR)为97.7 dB,峰值信噪比和失真比(SNDR)为94.8 dB,对应于176.8 dB的Schreier品质图(FoM)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 97.7-dB DR 12.3-μW 1-kHz Bandwidth 2<SUP>nd</SUP> Order Delta-sigma Modulator with a Fully Differential Class-AB Op-Amp using Floating Class-AB Control
This paper presents a 2SUPnd/SUP order modified feed-forward (FF) delta-sigma modulator. To reduce power consumption, the proposed analog-to-digital converter (ADC) adopts a class-AB op-amp for the first integrator since it shows an enhanced slew rate with low quiescent current. In addition, a 4-bit asynchronous successive approximation register (SAR) ADC which exhibits low power consumption is employed as a quantizer. A delay is incorporated into the feedback path for stable operation of the feedback loop. The prototype ADC is fabricated in a 28 nm CMOS process, and the core area is 0.095 mm2. It consumes 12.3 μW from 0.8 V (Analog)/0.85 V (Digital) supply voltages at an operating clock frequency of 512 kHz with an oversampling ratio (OSR) of 256. It achieves a dynamic range (DR) of 97.7 dB and a peak signal-to-noise and distortion ratio (SNDR) of 94.8 dB, corresponding to a Schreier figure-of-merit (FoM) of 176.8 dB.
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来源期刊
Journal of Semiconductor Technology and Science
Journal of Semiconductor Technology and Science ENGINEERING, ELECTRICAL & ELECTRONIC-PHYSICS, APPLIED
CiteScore
0.90
自引率
0.00%
发文量
40
审稿时长
6-12 weeks
期刊介绍: Journal of Semiconductor Technology and Science is published to provide a forum for R&D people involved in every aspect of the integrated circuit technology, i.e., VLSI fabrication process technology, VLSI device technology, VLSI circuit design and other novel applications of this mass production technology. When IC was invented, these people worked together in one place. However, as the field of IC expanded, our individual knowledge became narrower, creating different branches in the technical society, which has made it more difficult to communicate as a whole. The fisherman, however, always knows that he can capture more fish at the border where warm and cold-water meet. Thus, we decided to go backwards gathering people involved in all VLSI technology in one place.
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