Hao Jin, Sen Huang, Qimeng Jiang, Yingjie Wang, Jie Fan, Haibo Yin, Xinhua Wang, Ke Wei, Jianxun Liu, Yaozong Zhong, Qian Sun, Xinyu Liu
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引用次数: 0
摘要
摘要在p ++ -GaN/p-GaN/AlN/AlGaN/AlN/GaN/Si异质结构上,基于o3 - al2o3 /HfO 2 (5/15 nm)堆叠栅介质,展示了一种具有- 4.9 mA/mm高电流密度的增强模式(E-mode) GaN p沟道场效应晶体管(p- fet)。由于p ++ -GaN盖层,获得了良好的线性欧姆I−V特性,其接触电阻率(ρ c)为1.34 × 10−4 Ω·cm 2。通过原子层沉积生长的5 nm O - al - O - 3插入层有效地阻断了HfO - 2高k栅极介电介质的高栅极泄漏,使所制备的p- fet具有6 × 10.6的高I - ON / I - OFF比和显著降低的亚阈值摆幅(SS)。所提出的结构对于高能效的GaN互补逻辑(CL)电路是有吸引力的。
High-performance enhancement-mode GaN-based p-FETs fabricated with O3-Al2O3/HfO2-stacked gate dielectric
Abstract In this letter, an enhancement-mode (E-mode) GaN p-channel field-effect transistor (p-FET) with a high current density of −4.9 mA/mm based on a O 3 -Al 2 O 3 /HfO 2 (5/15 nm) stacked gate dielectric was demonstrated on a p ++ -GaN/p-GaN/AlN/AlGaN/AlN/GaN/Si heterostructure. Attributed to the p ++ -GaN capping layer, a good linear ohmic I − V characteristic featuring a low-contact resistivity ( ρ c ) of 1.34 × 10 −4 Ω·cm 2 was obtained. High gate leakage associated with the HfO 2 high- k gate dielectric was effectively blocked by the 5-nm O 3 -Al 2 O 3 insertion layer grown by atomic layer deposition, contributing to a high I ON / I OFF ratio of 6 × 10 6 and a remarkably reduced subthreshold swing (SS) in the fabricated p-FETs. The proposed structure is compelling for energy-efficient GaN complementary logic (CL) circuits.