A 116 TOPS/W Spatially Unrolled Time-Domain Accelerator Utilizing Laddered-Inverter DTC for Energy-Efficient Edge Computing in 65 nm

The increasing demand for high performance and energy efficiency in Artificial Neural Networks (ANNs) accelerators has driven a wide range of application-specific integrated circuits (ASICs). Besides, the rapid deployment of low-power IoT devices requires highly efficient computing, which as a result urges the need to explore low-power hardware implementations in different domains. This paper proposes a spatially unrolled time-domain accelerator that uses an ultra-low-power digital-to-time converter (DTC) while occupying an active area of 0.201 mm2. The proposed DTC is implemented using a Laddered, Inverter (LI) circuit, which consumes 3 $\times $ less power than the conventional inverter-based DTC and provides reliable performance across different process corners, supply voltages, and temperature variations. Post-synthesis results in 65nm CMOS show that the proposed core achieves a superior energy efficiency of 116 TOPS/W, a throughput of 4 GOPS, and an area efficiency of 20 GOPS/mm2. The proposed core improves energy efficiency by 2.4 - 47 $\times $ compared to prior time-domain accelerators.