Exploring the impact of initial design techniques on area, timing, and power in technology mapped designs: A case study on 32-bit arithmetic logic unit

This research paper investigates the influence of different initial design techniques on the area, timing, and power aspects of technology-mapped designs. As a practical case study, we undertake the design and analysis of a 32-bit arithmetic logic unit (ALU) utilizing two distinct adder approaches. The ALU, a fundamental component of all processors, comprises three major units: the Adder responsible for signed and unsigned number addition and subtraction, the Logic unit which handles bitwise logical operations, and the Shifter unit facilitates arithmetic and logical shift operations. The two adder designs are based on the ripple carry method (ALU_RCA) and the Sklansky method (ALU_SKL), respectively. The design and analysis process involved utilizing established toolsets from Cadence, including NCSIM for simulation and verification, RTL Compiler for logic synthesis, static timing analysis and power estimation, and SOC encounter tool for floorplanning and layout. Through this investigation, we aim to shed light on the varying performance implications of different initial design approaches in technology-mapped designs.