基于机器学习的栅极全能非薄片晶体管器件和电路建模综合技术

IF 1.8 Q3 MATERIALS SCIENCE, MULTIDISCIPLINARY
Rajat Butola;Yiming Li;Sekhar Reddy Kola
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引用次数: 0

摘要

机器学习(ML)在提高半导体器件紧凑建模领域的预测能力方面将发挥重要作用。基于ml的紧凑建模的一个主要优点是它能够捕获大型数据集中的复杂关系和模式。为此,本文提出了一种基于动态自适应神经网络(DANN)的新型设计方案,以快速、准确地建立紧凑模型(CM)。这个框架构成了一个强大而计算效率高的方法,并表现出紧急的动态行为。本文证明了基于机器学习的紧凑模型可以被设计成复制纳米器件传统紧凑模型的性能。在这项工作中,使用所提出的模型全面分析了栅极全能(GAA)纳米片(NS)器件的工艺变异性源。器件几何参数如通道长度、纳米片宽度和纳米片厚度作为输入特征馈送到DANN模型。自适应神经网络通过根据输入特征更新模型的权值进行动态学习,实现神经网络权值的精确收敛。该模型预测NS器件电特性的错误率小于1%。该模型还在数字电路设计(如逆变器和逻辑门)的仿真中得到了实现和验证。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Comprehensive Technique Based on Machine Learning for Device and Circuit Modeling of Gate-All-Around Nanosheet Transistors
Machine learning (ML) is poised to play an important part in advancing the predicting capability in semiconductor device compact modeling domain. One major advantage of ML-based compact modeling is its ability to capture complex relationships and patterns in large datasets. Therefore, in this paper a novel design scheme based on dynamically adaptive neural network (DANN) is proposed to develop fast and accurate compact model (CM). This framework constitutes a powerful yet computationally efficient methodology and exhibits emergent dynamic behaviors. This paper demonstrates that the compact model based on ML can be designed to replicate the performance of conventional compact model for nanodevices. For this work, gate-all-around (GAA) nanosheet (NS) device characteristics are comprehensively analyzed for process variability sources using the proposed model. The device geometry parameters such as channel length, nanosheet width and nanosheet thickness are fed as input features to the DANN model. The adaptive neural network learns dynamically by updating weights of the model in accordance with the input features and achieves accurate neural weight convergence. The proposed model predicted the electrical characteristics of NS devices with less than 1% error rate. The model is also implemented and validated for the simulations of digital circuit designs such as inverter, and logic gates.
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来源期刊
CiteScore
3.90
自引率
17.60%
发文量
10
审稿时长
12 weeks
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