(Invited) Sequential 3D Integration of Ge Transistors on Si CMOS

To keep the scaling progress going, we must go three dimensional (3D). This paper outlines some technology challenges and solutions to integrate Ge p-type MOSFETs sequentially on Si CMOS. Such a solution addresses the grand challenge to enable increased device density. However, the device itself does not have to scale but at the same time innovative solutions are suggested for low supply voltage operation enabling energy efficient integrated circuits (ICs) that will not be dominated by energy consumption in interconnects. By stacking the transistors on top of each other, and connecting them with inter-tier via, the density of transistors per unit area increases. This approach demands that transistors are fabricated at a lower temperature than today’s Si CMOS technology. Here, we have focused on Ge based transistors, which have an inherently lower process temperature compared to Si transistors. Several technological and design breakthroughs towards realizing Ge based sequential 3D circuits are discussed.