Physical-Layer Security for Energy-Constrained Integrated Systems: Challenges and Design Perspectives

The expanding scale and growing connectivity of Internet of Things (IoT) devices coincide with the emergence of next-generation communication technologies. These devices serve various purposes, including communication, manufacturing, biomedical, and environmental monitoring. However, the increasing number of connected devices raises concerns about data security and integrity. Previous research has highlighted the severe consequences of security inadequacies, shown by incidents involving biomedical devices [1] , [2] , [3] as an example. Nevertheless, due to resource constraints like power, hardware complexity, and latency, digital cryptography is not universally suitable for these devices [4] , [5] , [6] . An alternative is embedding physical-layer security (PLS) measures. Diverse countermeasures within the physical layer have been explored, including wireless network security [4] , [5] , [6] , [7] , [8] , [9] and resistance against side-channel attacks (SCAs) [10] , [11] , [12] . This study reviews threat modeling for PLS, underlining its significance and emphasizing its similarities and distinctions from conventional security threat models. We then investigate two commonly employed adversarial techniques: 1) eavesdropping and 2) SCAs. This exploration involves an investigation of distinct security approaches, alongside an evaluation of their associated threat models and tradeoffs. While PLS techniques address the aforementioned resource and latency constraints, they do not universally apply to all devices. Ultralow-power or ultralow-latency devices might necessitate balancing security with performance. However, the absence of a standardized framework in the realm of PLS poses challenges for designers in comparing and selecting the most fitting approach. To conclude, this work provides suggestions for addressing current gaps and enhancing the field of PLS.