使用静态分析增强 HLS 安全性

IF 1.7 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Embedded Systems Letters Pub Date : 2023-11-03 DOI:10.1109/LES.2023.3329417

Luca Collini;Joey Ah-Kiow;Christian Pilato;Ramesh Karri;Benjamin Tan

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引用次数: 0

摘要

由于现代集成电路的复杂性不断增加，高级综合（HLS）正成为硬件设计的一项关键技术。HLS 使用优化技术来帮助探索设计空间。然而，其中一些优化可能会引入安全漏洞。我们提出了一种方法，利用静态分析来识别 HLS 生成代码中的一类弱点。我们表明，其中一些弱点可以通过自动生成 HLS 指令来纠正。我们通过比较静态分析结果和形式验证来评估我们的方法。我们的结果表明，静态方法与形式方法具有相同的准确性，而速度却要快上 3 到 200 倍。

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Using Static Analysis for Enhancing HLS Security

Due to the increasing complexity of modern integrated circuits, high-level synthesis (HLS) is becoming a key technology in hardware design. HLS uses optimizations to assist during design space exploration. However, some of them can introduce security weaknesses. We propose an approach that leverages static analysis to identify a class of weaknesses in HLS-generated code. We show that some of these weaknesses can be corrected through the automatic generation of HLS directives. We evaluate our approach by comparing the static analysis results with formal verification. Our results show that the static approach has the same accuracy as formal methods while being

$3\times $

$200\times $

faster.

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来源期刊

IEEE Embedded Systems Letters Engineering-Control and Systems Engineering

CiteScore

3.30

自引率

0.00%

发文量

期刊介绍： The IEEE Embedded Systems Letters (ESL), provides a forum for rapid dissemination of latest technical advances in embedded systems and related areas in embedded software. The emphasis is on models, methods, and tools that ensure secure, correct, efficient and robust design of embedded systems and their applications.