路由器通信电子硬件芯片设计

IF 0.8 4区 综合性期刊 Q3 MULTIDISCIPLINARY SCIENCES
Prateek Agarwal, Tanuj Kumar Garg, Adesh Kumar
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引用次数: 0

摘要

与标量cpu相比,终端缩放指的是使用异构多处理器片上系统。当应用程序在适当的处理器元素(pe)上运行时,它所进行的计算消耗的能量更少,这些处理器元素已经为困难的操作进行了增强。然而,随着pe的增加,沟通变得越来越重要。NoC的片上互连技术使用了来自网络的按比例缩小的通信技术。路由器是一种物理或虚拟设备,在两个或多个分组交换处理器网络之间充当共享形式的网关。该路由器用于SoC中的NoC连接和相关的路由器-路由器通信设计。本文介绍了二维路由器的硬件芯片设计,采用独立芯片和集成NoC实现两台路由器之间的路由器-路由器芯片通信。路由器硬件芯片的设计是在赛灵思集成系统环境(ISE) 14.7软件中完成的。Modelsim 10.0用于利用从所有输入/输出端口发送的数据包进行逻辑验证。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

Electronics Hardware Chip Design for Router–Router Communication

Electronics Hardware Chip Design for Router–Router Communication

In contrast to scalar CPUs, end scaling refers to the use of heterogeneous multiprocessor systems-on-chip. Calculations made by an application consume less energy when it is run on the appropriate processor elements (PEs) that have been enhanced for difficult operations. However, as the PEs are increased, communication becomes more and more important. The on-chip interconnect technology of NoC uses scaled-down communication techniques from networks. A router is a physical or virtual device that acts as a shared form of gateway for material between two or more packet-switched processor networks. The router is used for NoC connection in SoC and concerned designs for router–router communication. This paper presents the hardware chip design of the 2D routers and employs router–router chip communication between two routers using independent chips and integrated NoC. The router hardware chip design is done in Xilinx Integrated System Environment (ISE) 14.7 software. Modelsim 10.0 is used for logic verification utilizing data packets sent from all input/output ports.

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来源期刊
CiteScore
2.60
自引率
0.00%
发文量
37
审稿时长
>12 weeks
期刊介绍: To promote research in all the branches of Science & Technology; and disseminate the knowledge and advancements in Science & Technology
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