浮点混合FPGA中粗粒度单元的优化

Chi Wai Yu, Alastair M. Smith, W. Luk, P. Leong, S. Wilton
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引用次数: 13

摘要

介绍了一种优化混合FPGA中粗粒度浮点单元(fpu)的新方法。我们使用公共子图提取来确定fpu中的浮点加/减(fa),乘(fm)和词块(wb)的数量。我们首先研究了在一组浮点基准电路中所选择的FPU子图的面积、速度和利用率权衡。然后,我们从面积、速度和路由资源方面探讨了fpu的密度和灵活性对系统的影响。通过考虑体系结构和系统级问题,我们得到了一个优化的粗粒度FPU。结果表明:(1)在系统中嵌入更多类型的粗粒度FPU最多可使延迟增加21.3%;(2)嵌入高密度子图可使系统面积减少27.4%;(3)高密度子图所需路由资源减少14.8%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Optimizing coarse-grained units in floating point hybrid FPGA
This paper introduces a novel methodology to optimize coarse-grained floating point units (FPUs) in a hybrid FPGA. We employ common subgraph extraction to determine the number of floating point adders/subtracters (FAs), multipliers (FMs) and wordblocks (WBs) in the FPUs. We flrst study the area, speed and utilization trade-off of the selected FPU subgraphs in a set of floating point benchmark circuits. We then explore the impact of density and flexibility of FPUs on the system in terms of area, speed and routing resources. We derive an optimized coarse-grained FPU by considering both architectural and system level issues. The results show that: (1) embedding more types of coarse-grained FPU in the system causes at most 21.3% increase in delay, (2) the area of the system can be reduced by 27.4% by embedding high density subgraphs, (3) the high density subgraphs requires 14.8% fewer routing resources.
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