{"title":"基于DDR的高效高速多通道数据采集的硬件设计","authors":"Priyanka Chauhan, Karan Jasani, Dippal Israni, Ashwin Makwana","doi":"10.1109/I2CT.2017.8226133","DOIUrl":null,"url":null,"abstract":"A Data Acquisition System (DAQs) is an indispensable part to receive, store and further analysis of data. This paper focuses on Data Acquisition from multiple channels using Dual Data Rate (DDR) techniques. Multiple Channels of data source which are source synchronous are initially configured using Serial Peripheral Interface (SPI) commands. The Proposed technique gives an advantage of storing data received from multiple channels in parallel form. The proposed approach is divided into two parts. First is to acquire data from multiple channels of single data source into XILINX sparten-6 Field Programmable Gate Array (FPGA) followed by storing the same onto high speed storage device such as Static Random Access Memory (SRAM).","PeriodicalId":343232,"journal":{"name":"2017 2nd International Conference for Convergence in Technology (I2CT)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Hardware design of an efficient high speed multi channel data acquisition using DDR\",\"authors\":\"Priyanka Chauhan, Karan Jasani, Dippal Israni, Ashwin Makwana\",\"doi\":\"10.1109/I2CT.2017.8226133\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A Data Acquisition System (DAQs) is an indispensable part to receive, store and further analysis of data. This paper focuses on Data Acquisition from multiple channels using Dual Data Rate (DDR) techniques. Multiple Channels of data source which are source synchronous are initially configured using Serial Peripheral Interface (SPI) commands. The Proposed technique gives an advantage of storing data received from multiple channels in parallel form. The proposed approach is divided into two parts. First is to acquire data from multiple channels of single data source into XILINX sparten-6 Field Programmable Gate Array (FPGA) followed by storing the same onto high speed storage device such as Static Random Access Memory (SRAM).\",\"PeriodicalId\":343232,\"journal\":{\"name\":\"2017 2nd International Conference for Convergence in Technology (I2CT)\",\"volume\":\"34 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 2nd International Conference for Convergence in Technology (I2CT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/I2CT.2017.8226133\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 2nd International Conference for Convergence in Technology (I2CT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/I2CT.2017.8226133","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Hardware design of an efficient high speed multi channel data acquisition using DDR
A Data Acquisition System (DAQs) is an indispensable part to receive, store and further analysis of data. This paper focuses on Data Acquisition from multiple channels using Dual Data Rate (DDR) techniques. Multiple Channels of data source which are source synchronous are initially configured using Serial Peripheral Interface (SPI) commands. The Proposed technique gives an advantage of storing data received from multiple channels in parallel form. The proposed approach is divided into two parts. First is to acquire data from multiple channels of single data source into XILINX sparten-6 Field Programmable Gate Array (FPGA) followed by storing the same onto high speed storage device such as Static Random Access Memory (SRAM).