Hyeonchan Lim, Tae Hyun Kim, Seunghwan Kim, Sungho Kang
{"title":"基于机器学习的扫描链故障诊断","authors":"Hyeonchan Lim, Tae Hyun Kim, Seunghwan Kim, Sungho Kang","doi":"10.1109/ISOCC50952.2020.9333074","DOIUrl":null,"url":null,"abstract":"In order to improve yield of nanometer-scale chips, scan-based test and diagnosis are important. However, the scan chain can be subject to defects due to large hardware incurred by itself, which accounts for considerable portion of total chip area. Hence, scan chain test and diagnosis has played a critical role in recent years. In this paper, an efficient scan chain diagnosis method based on two-stage neural networks is proposed for not only stuck-at fault but also transition fault. Experimental results on benchmark circuits show that the proposed method is 10% more accurate than a previous work and CPU time for training the neural networks is also reduced dramatically.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Diagnosis of Scan Chain Faults Based-on Machine-Learning\",\"authors\":\"Hyeonchan Lim, Tae Hyun Kim, Seunghwan Kim, Sungho Kang\",\"doi\":\"10.1109/ISOCC50952.2020.9333074\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In order to improve yield of nanometer-scale chips, scan-based test and diagnosis are important. However, the scan chain can be subject to defects due to large hardware incurred by itself, which accounts for considerable portion of total chip area. Hence, scan chain test and diagnosis has played a critical role in recent years. In this paper, an efficient scan chain diagnosis method based on two-stage neural networks is proposed for not only stuck-at fault but also transition fault. Experimental results on benchmark circuits show that the proposed method is 10% more accurate than a previous work and CPU time for training the neural networks is also reduced dramatically.\",\"PeriodicalId\":270577,\"journal\":{\"name\":\"2020 International SoC Design Conference (ISOCC)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-10-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC50952.2020.9333074\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC50952.2020.9333074","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Diagnosis of Scan Chain Faults Based-on Machine-Learning
In order to improve yield of nanometer-scale chips, scan-based test and diagnosis are important. However, the scan chain can be subject to defects due to large hardware incurred by itself, which accounts for considerable portion of total chip area. Hence, scan chain test and diagnosis has played a critical role in recent years. In this paper, an efficient scan chain diagnosis method based on two-stage neural networks is proposed for not only stuck-at fault but also transition fault. Experimental results on benchmark circuits show that the proposed method is 10% more accurate than a previous work and CPU time for training the neural networks is also reduced dramatically.