将NW-FET建模集成到SET-FET电路中

2018 Spanish Conference on Electron Devices (CDE) Pub Date : 2018-11-01 DOI:10.1109/CDE.2018.8596986

A. del Moral, E. Amat, J. Bausells, F. Pérez-Murano

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引用次数: 0

摘要

本文对垂直纳米线场效应晶体管(FET)的电学特性进行了研究。模拟的NW-FET的输出电流根据多个参数进行了优化，以增强其在亚阈值区域的行为。为了提高器件的平均性能和稳定性，还对变异性容限进行了分析。建立了NW-FET的过程仿真模型，以进一步实现其可制造性和在混合SET-FET电路中的应用。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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NW-FET Modelling to be Integrated in a SET-FET Circuit

In this work, an electrical study of a vertical nanowire (NW)-based Field Effect Transistor (FET) is presented. The resulting output current from the modelled NW-FET is optimized in terms of multiple parameters, in order to enhance the behavior at subthreshold regime. Variability tolerance is analyzed as well, in order to attain improvements concerning average device performance and stability. A process simulation model for a NW-FET is built in perspective for its further manufacturability and implementation into hybrid SET-FET circuits.

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2018 Spanish Conference on Electron Devices (CDE)

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