Using SOI to achieve low-power consumption in digital

SOI offers an efficient static and dynamic power reduction through V/sub dd/ reduction without sacrificing speed performance. This V/sub dd/ reduction may be combined or not with other circuit techniques: MTCMOS where high-V/sub t/ transistors are connected in series between the core logic and ground/V/sub dd/, gated clock cells where the clock is automatically diabled and not propagated. A low-power SOI circuit may be designed by gathering several blocks using different V/sub dd/ values depending on the speed requirement for each block. In such a case level-shifters are used to adapt the V/sub dd/ difference between the blocks (V/sub dd1/ output to V/sub dd2/ input and V/sub dd2/ output to V/sub dd/1 input). This requires the implementation of several power supply sources at system level. Implementing these techniques adds more design complexity and EDA tools must be able to support them. Making a comparison between bulk and SOI is not an easy task and it cannot be done only at transistor or cell level. The best way is to compare the results(speed, P/sub stat/, P/sub dyn/, area) obtained when a circuit is synthesized, placed and routed using bulk or SOI libraries, including the memories.