N. Sillon, D. Henry, J. Souriau, J. Brun, H. Boutry, S. Chéramy
{"title":"晶圆级封装的新趋势","authors":"N. Sillon, D. Henry, J. Souriau, J. Brun, H. Boutry, S. Chéramy","doi":"10.1109/IITC.2009.5090390","DOIUrl":null,"url":null,"abstract":"We present in this paper the two generic integration schemes developed at Leti, aiming to address two opposite industrial needs. The first scheme, based on TSV free Via Belt technology, allows wafer level integration of highly heterogeneous systems taking into account different technologies, wafer and die sizes and mainly targets enduser companies looking for generic technologies. The second one, based on TSV WLP and active silicon interposer, mainly addresses the IDMs needs. Main technological bricks related to both schemes are presented and validated through specific demonstrators.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"70 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"New trends in wafer level packaging\",\"authors\":\"N. Sillon, D. Henry, J. Souriau, J. Brun, H. Boutry, S. Chéramy\",\"doi\":\"10.1109/IITC.2009.5090390\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present in this paper the two generic integration schemes developed at Leti, aiming to address two opposite industrial needs. The first scheme, based on TSV free Via Belt technology, allows wafer level integration of highly heterogeneous systems taking into account different technologies, wafer and die sizes and mainly targets enduser companies looking for generic technologies. The second one, based on TSV WLP and active silicon interposer, mainly addresses the IDMs needs. Main technological bricks related to both schemes are presented and validated through specific demonstrators.\",\"PeriodicalId\":301012,\"journal\":{\"name\":\"2009 IEEE International Interconnect Technology Conference\",\"volume\":\"70 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE International Interconnect Technology Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IITC.2009.5090390\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE International Interconnect Technology Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2009.5090390","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
We present in this paper the two generic integration schemes developed at Leti, aiming to address two opposite industrial needs. The first scheme, based on TSV free Via Belt technology, allows wafer level integration of highly heterogeneous systems taking into account different technologies, wafer and die sizes and mainly targets enduser companies looking for generic technologies. The second one, based on TSV WLP and active silicon interposer, mainly addresses the IDMs needs. Main technological bricks related to both schemes are presented and validated through specific demonstrators.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
