WSI体系结构的一个神经计算机模块

1990 Proceedings. International Conference on Wafer Scale Integration Pub Date : 1990-01-23 DOI:10.1109/ICWSI.1990.63892

U. Ramacher, M. Wesseling, K. Goser

{"title":"WSI体系结构的一个神经计算机模块","authors":"U. Ramacher, M. Wesseling, K. Goser","doi":"10.1109/ICWSI.1990.63892","DOIUrl":null,"url":null,"abstract":"Discusses application and technology related constraints on the implementation of neurocomputing systems on a wafer. The resulting neurocomputer architecture builds on the experience obtained with a 42 cm/sup 2/ soft-configured chip which carries a 2-dimensional array of multipliers in CMOS. The architecture is specially adapted to pattern recognition of video images by means of generalized multilayer-perceptrons.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"WSI architecture of a neurocomputer module\",\"authors\":\"U. Ramacher, M. Wesseling, K. Goser\",\"doi\":\"10.1109/ICWSI.1990.63892\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Discusses application and technology related constraints on the implementation of neurocomputing systems on a wafer. The resulting neurocomputer architecture builds on the experience obtained with a 42 cm/sup 2/ soft-configured chip which carries a 2-dimensional array of multipliers in CMOS. The architecture is specially adapted to pattern recognition of video images by means of generalized multilayer-perceptrons.<<ETX>>\",\"PeriodicalId\":206140,\"journal\":{\"name\":\"1990 Proceedings. International Conference on Wafer Scale Integration\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-01-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1990 Proceedings. International Conference on Wafer Scale Integration\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICWSI.1990.63892\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1990 Proceedings. International Conference on Wafer Scale Integration","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICWSI.1990.63892","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 9

摘要

讨论了在晶圆上实现神经计算系统的应用和技术限制。由此产生的神经计算机架构建立在42cm /sup /软配置芯片上获得的经验之上，该芯片在CMOS中携带二维乘法器阵列。该体系结构特别适用于利用广义多层感知器对视频图像进行模式识别。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

WSI architecture of a neurocomputer module

Discusses application and technology related constraints on the implementation of neurocomputing systems on a wafer. The resulting neurocomputer architecture builds on the experience obtained with a 42 cm/sup 2/ soft-configured chip which carries a 2-dimensional array of multipliers in CMOS. The architecture is specially adapted to pattern recognition of video images by means of generalized multilayer-perceptrons.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

1990 Proceedings. International Conference on Wafer Scale Integration

自引率

0.00%

发文量