P. Agnello, T. Newman, E. Crabbé, S. Subbanna, É. Ganin, L. Liebmann, J. Comfort, D. Sunderland
{"title":"在200毫米全CMOS工艺中实现低于0.1 /spl mu/m的电通道长度的相位边缘光刻","authors":"P. Agnello, T. Newman, E. Crabbé, S. Subbanna, É. Ganin, L. Liebmann, J. Comfort, D. Sunderland","doi":"10.1109/VLSIT.1995.520867","DOIUrl":null,"url":null,"abstract":"In this work a deep-UV stepper is used in conjunction with a phase edge mask to define sub 0.1 /spl mu/m electrical channel length gates in a 200 mm integrated CMOS process. Conventional binary intensity mask deep-UV and mid-UV lithography are other used for other levels. We demonstrate excellent channel length control with the phase edge technique, at channel lengths here-to-fore only achievable by e-beam or X-ray lithography.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Phase edge lithography for sub 0.1 /spl mu/m electrical channel length in a 200 mm full CMOS process\",\"authors\":\"P. Agnello, T. Newman, E. Crabbé, S. Subbanna, É. Ganin, L. Liebmann, J. Comfort, D. Sunderland\",\"doi\":\"10.1109/VLSIT.1995.520867\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work a deep-UV stepper is used in conjunction with a phase edge mask to define sub 0.1 /spl mu/m electrical channel length gates in a 200 mm integrated CMOS process. Conventional binary intensity mask deep-UV and mid-UV lithography are other used for other levels. We demonstrate excellent channel length control with the phase edge technique, at channel lengths here-to-fore only achievable by e-beam or X-ray lithography.\",\"PeriodicalId\":328379,\"journal\":{\"name\":\"1995 Symposium on VLSI Technology. Digest of Technical Papers\",\"volume\":\"44 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-06-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1995 Symposium on VLSI Technology. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1995.520867\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1995 Symposium on VLSI Technology. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1995.520867","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Phase edge lithography for sub 0.1 /spl mu/m electrical channel length in a 200 mm full CMOS process
In this work a deep-UV stepper is used in conjunction with a phase edge mask to define sub 0.1 /spl mu/m electrical channel length gates in a 200 mm integrated CMOS process. Conventional binary intensity mask deep-UV and mid-UV lithography are other used for other levels. We demonstrate excellent channel length control with the phase edge technique, at channel lengths here-to-fore only achievable by e-beam or X-ray lithography.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
