提高65nm Cu/Low-k工艺可靠性的综合研究

C. Liao, Z. Gan, Yuehua Wu, K. Zheng, R. Guo, L. F. Zhang, J. Ning
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引用次数: 1

摘要

随着Cu/低k互连器件尺寸的不断扩大,BEOL的可靠性成为越来越重要的问题,包括低k电介质的电迁移(EM)、应力迁移(SM)、线间泄漏、击穿和时间相关介质击穿(TDDB)特性以及等离子体过程诱导损伤(P2ID)。本文综述了65nm Cu/low-k工艺的BEOL可靠性改进。提高可靠性的措施包括对金属尺寸均匀性、Cu - cap层界面完整性(SiCN)和通孔底部完整性的工艺控制;等离子体控制前金属介质(PMD)沉积,铜势垒沉积前的预清洁和铝衬垫的钝化蚀刻。还将讨论各自改进的相应物理机制。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Comprehensive study of reliability improvement for 65nm Cu/Low-k process
BEOL reliability becomes increasing important issues as device dimensions are scaled for the Cu/low-k interconnects, including electromigration (EM), stress migration (SM), inter-line leakage, breakdown and time-dependent dielectric breakdown (TDDB) characteristics of low-k dielectrics, and plasma-process induced damage (P2ID). This paper gives a summary of the BEOL reliability improvement for the 65nm Cu/low-k process. The efforts for the reliability improvement include process control for metal dimension uniformity, the interface integrity between Cu and cap layer (SiCN), and via bottom integrity; and plasma control for the pre-metal dielectric (PMD) deposition, pre-clean before Cu barrier deposition and passivation etching for Al pad. The corresponding physical mechanisms for the respective improvements will also be discussed.
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