考虑目标阻抗的高性能微处理器封装配电系统设计分析

IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565) Pub Date : 2001-10-29 DOI:10.1109/EPEP.2001.967662

O.P. Mandhana

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引用次数: 11

摘要

本文提出了一种有效的设计方法，使高性能微处理器内核的输出阻抗等于或小于目标阻抗，从而降低内核中频噪声。在对分组配电网络(PPDN)集总模型进行频域分析的基础上，提出了一种系统估计分组配电网络分布模型中去耦电容电容及其相关寄生特性的方法。分析方法的仿真结果与分布式PPDN模型的SPICE仿真结果具有良好的相关性，可以降低核心处的输出阻抗。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design oriented analysis of package power distribution system considering target impedance for high performance microprocessors

This paper presents an efficient design methodology to realize the output impedance at the high performance microprocessor core equal to or less than the target impedance to reduce the mid-frequency core noise. Based on the frequency domain analysis of the lumped model of the package power distribution network (PPDN), a systematic method of estimating capacitance and associated parasitics of decoupling capacitors used in the distributed model of the PPDN is described. The simulation results of the analytical method show good correlation with the SPICE simulation results of the distributed PPDN model to reduce the output impedance at the core.

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IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)

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