Digital Clock and Data Recovery Circuits for Optical Links

Clock and Data Recovery (CDR) circuits perform the function of recovering clock and re-timing received data in optical links. These CDRs must be capable of tolerating large input jitter (high JTOL), filter input jitter (low JTRAN with no jitter peaking) and in burst-mode applications be capable of phase locking in a very short time. In this paper, we elucidate these design tradeoffs and present various CDR architectures that can overcome them. Specifically, D/PLL CDR architecture that achieves high JTOL, low JTRAN, and no jitter peaking is described. A new burst-mode CDR that can lock instantaneously while filtering input jitter is also discussed.