纳米级CMOS数字技术α功率MOSFET模型的图形化分析

2020 6th International Conference on Signal Processing and Communication (ICSC) Pub Date : 2020-03-01 DOI:10.1109/ICSC48311.2020.9182772

Shruti Kalra

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引用次数: 2

摘要

通常观察到，用于构建基本数字CMOS块设计方法的传统分析方程要么是物理的，要么是基于经验的。基于Sakurai-Newton (SN) α-功率的MOSFET模型是几十年来用于模拟亚微米技术节点漏极电流的最简单的经验模型之一。本文介绍了作者将基于α-功率的MOSFET模型与jesper - memlink - wallinga (JMW)表示法连接起来的教学努力，JMW表示法恰好是直观捕捉长沟道晶体管基本工作的流行方法。将SN模型与JMW表示法相结合，还可以直观地捕捉短沟道晶体管的基本工作原理。图形化表示的结果与基于解析物理的MOSFET模型和行业标准BSIM的22nm技术节点进行了比较。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A Graphical Insight into α Power MOSFET Model for Nanoscale CMOS Digital Technologies

It has been usually observed that conventional analytical equations utilized for building design methodologies for fundamental digital CMOS blocks are either physics or empirical based. Sakurai-Newton (SN) α-power based MOSFET model is one of the simplest empirical model that has been utilized from decades to model drain current at submicron technology node. This paper presents the pedagogical effort of the author to connect α-power based MOSFET model with Jesper-Memelink-Wallinga (JMW) representation which happens to be a popular approach for visually capturing the basic operation of long channel transistor. Connecting SN model and JMW representation enables us to visually capture the basic operation of short channel transistor also. The results obtained from the graphical representation are compared with analytical physics based MOSFET model and industry standard BSIM upto 22nm technology node.

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2020 6th International Conference on Signal Processing and Communication (ICSC)

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