具有低噪声放大器和高通σ - δ调制器的模拟前端电路,用于脑电图或ECoG采集系统

Jia-Hua Hong, Ming-Chun Liang, Ming-Yang Haung, T. Tsai, Q. Fang, Shuenn-Yuh Lee
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引用次数: 11

摘要

本文提出了一种模拟前端(AFE)电路,该电路仅包括一个具有斩波技术的低噪声放大器和一个高通sigma-delta调制器(HPSDM),可作为脑电图或皮质电图(ECoG)信号采集系统的传感电路。该低噪声放大器采用带反馈伪电阻和电容的差分放大器实现,闭环增益为20 V/V, CMRR为109.6 dB。HPSDM采用前馈结构,阶数为3,过采样比为128,采样频率为51.2 kHz,采用1位量化器。整个AFE电路采用TSMC 0.18 μm 1P6M CMOS工艺,电源电压为1.2 V,功耗为28.7 μW。在ECoG信号的最大范围内,整个AFE电路的仿真信噪比和SFDR分别为70.8和73 dB。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Analog front-end circuit with low-noise amplifier and high-pass sigma-delta modulator for an EEG or ECoG acquisition system
The present paper proposes an analog front-end (AFE) circuit, including only one low-noise amplifier with chopping techniques and one high-pass sigma-delta modulator (HPSDM), which can be applied as a sensing circuit for electroencephalogram or electrocorticogram (ECoG) signal acquisition systems. The low-noise amplifier, which has a close-loop gain of 20 V/V and CMRR of 109.6 dB, is implemented by a differential difference amplifier with feedback pseudo-resistors and capacitors. The HPSDM is implemented in a feed-forward architecture with an order of 3, an oversampling ratio of 128, and a 1-bit quantizer under a sampling frequency of 51.2 kHz. The TSMC 0.18 μm 1P6M CMOS process is used in the entire AFE circuit with a supply voltage of 1.2 V and power consumption of 28.7 μW. Within the maximum range of ECoG signals, the simulated SNR and SFDR of the entire AFE circuits are 70.8 and 73 dB, respectively.
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