多媒体RISC处理器的16位并行MAC架构

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI:10.1109/SIPS.1998.715773

Ichiro Kuroda, Eri Murata, Kouhei, Nadehara, Kazumasa Suzukit, T. Arai, Atsushi Okamurat

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引用次数: 12

摘要

本文提出了一种基于200 mhz、1.6 gops多媒体RISC处理器的并行MAC(乘累加)架构。处理器的数据路径体系结构旨在实现数据传输和SIMD并行算术运算的并行执行。SIMD并行16位MAC指令采用对称舍入方案，最大限度地提高了18位累积的精度。在64位数据路径上的并行16位MAC指令被证明可以有效地用于DSP应用，例如多媒体RISC处理器中的卷积。采用对称四舍五入的并行MAC指令，满足IEEE 1180的二维逆离散余弦变换(2D-IDCT)仅需202个周期即可实现。

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A 16-bit parallel MAC architecture for a multimedia RISC processor

This paper presents a parallel MAC (multiply-accumulation) architecture designed for DSP applications on a 200-MHz, 1.6-GOPS multimedia RISC processor. The datapath architecture of the processor is designed to realize parallel execution of a data transfer and SIMD parallel arithmetic operations. SIMD parallel 16-bit MAC instructions are introduced with a symmetric rounding scheme which maximizes the accuracy of the 18-bit accumulation. This parallel 16-bit MAC instruction on a 64-bit datapath is shown to be efficiently utilized for DSP applications such as convolution in the multimedia RISC processor. By using the parallel MAC instruction with the symmetric rounding scheme, the two-dimensional inverse discrete cosine transform (2D-IDCT) which satisfies IEEE 1180 can be implemented in 202 cycles.

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来源期刊

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)

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