延时9ns- hit的32K字节缓存宏的电路设计

Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI:10.1109/VLSIC.1989.1037482

K. Nogami, T. Sakurai, K. Sawada, K. Sakaue, Y. Miyazawa, S. Tanaka, Y. Hiruta, K. Katoh, T. Takayanagi, T. Shirotopi, Y. Itoh, M. Uchma, T. Hzuka

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引用次数: 1

摘要

在精简信息集计算机(RISCJ)被证明可以有效地提高CPU性能后，人们开始尝试通过在同一芯片中加入缓存来进一步提高CPU性能。然而，以前报告的缓存大小被限制在2K bym以内。这不足以获得95%以上的命中率。本文描述了一个32K字节的缓存宏，并在同一芯片上实现了一个实验性的RISC。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Circuit design of a 9ns-HIT-delay 32K byte cache macro

Introduction After a Reduced Insrmction Set Computer (RISCJ was shown to be effective in increasing CPU perfomnceIl1, s e v d attempls have teen made to funher improve the CPU performance by including cache memory an the same chipl21. However, the formerly reported cache size is limited up to 2K bym. which is not sufficient to obtain more than 95% hit rate. This paper describes a 32K byte cache macro with an erperimmml RISC implemented on the Same chip.

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Symposium 1989 on VLSI Circuits

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