62-GHz 24mw静态SiGe分频器

Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004. Pub Date : 2004-09-08 DOI:10.1109/SMIC.2004.1398153

H. Knapp, M. Wurzer, K. Aufinger, J. Bock, T. Meister

{"title":"62-GHz 24mw静态SiGe分频器","authors":"H. Knapp, M. Wurzer, K. Aufinger, J. Bock, T. Meister","doi":"10.1109/SMIC.2004.1398153","DOIUrl":null,"url":null,"abstract":"We present a static frequency divider with a divide ratio of 16. The circuit is realized in current-mode logic (CML) and operates up to a maximum frequency of 62 GHz. The first master-slave flip-flop uses shunt peaking and consumes only 4 mW from a 2 V supply. The total supply current including all four divider stages and buffers is 12 mA. The circuit is manufactured in a 200-GHz f/sub T/ SiGe bipolar process.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"62-GHz 24-mW static SiGe frequency divider\",\"authors\":\"H. Knapp, M. Wurzer, K. Aufinger, J. Bock, T. Meister\",\"doi\":\"10.1109/SMIC.2004.1398153\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a static frequency divider with a divide ratio of 16. The circuit is realized in current-mode logic (CML) and operates up to a maximum frequency of 62 GHz. The first master-slave flip-flop uses shunt peaking and consumes only 4 mW from a 2 V supply. The total supply current including all four divider stages and buffers is 12 mA. The circuit is manufactured in a 200-GHz f/sub T/ SiGe bipolar process.\",\"PeriodicalId\":288561,\"journal\":{\"name\":\"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.\",\"volume\":\"44 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SMIC.2004.1398153\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMIC.2004.1398153","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

提出了一种分频比为16的静态分频器。该电路采用电流模式逻辑(CML)实现，工作频率最高可达62 GHz。第一个主从触发器使用分流调峰，从2v电源只消耗4mw。包括所有四个分压器级和缓冲器在内的总电源电流为12毫安。该电路采用200 ghz f/sub T/ SiGe双极工艺制造。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

62-GHz 24-mW static SiGe frequency divider

We present a static frequency divider with a divide ratio of 16. The circuit is realized in current-mode logic (CML) and operates up to a maximum frequency of 62 GHz. The first master-slave flip-flop uses shunt peaking and consumes only 4 mW from a 2 V supply. The total supply current including all four divider stages and buffers is 12 mA. The circuit is manufactured in a 200-GHz f/sub T/ SiGe bipolar process.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.

自引率

0.00%

发文量