奇偶网络的最佳测试模式

AFIPS '70 (Fall) Pub Date : 1899-12-30 DOI:10.1145/1478462.1478472

D. C. Bossen, D. Ostapko, Arvind M. Patel

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引用次数: 41

摘要

与数字计算机的错误检测和/或纠错电路有关的逻辑通常包含计算一组位的奇偶校验的部分。由异或门组成的树结构用于执行此计算。类似于任何其他电路，这个奇偶校验树的操作容易发生故障。本报告介绍了在奇偶校验树中测试故障的过程。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Optimum test patterns for parity networks

The logic related to the error detecting and/or correcting circuitry of digital computers often contains portions which calculate the parity of a collection of bits. A tree structure composed of Exclusive-OR gates is used to perform this calculation. Similar to any other circuitry, the operation of this parity tree is subject to malfunctions. A procedure for testing malfunctions in a parity tree is presented in this report.

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AFIPS '70 (Fall)

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