{"title":"Viterbi解码的运行时可重构体系结构","authors":"Juan M. Campos, René Cumplido","doi":"10.1109/ICEEE.2006.251908","DOIUrl":null,"url":null,"abstract":"This paper presents the design and implementation of a runtime reconfigurable architecture for Viterbi decoding with a high throughput rate suitable for software defined radio (SDR). SDR is a radio that is substantially defined in software and whose physical layer behavior can be significantly altered through changes to its software. The architecture can be reconfigured to decode convolutionally coded data with constraint lengths from 3 to 7 and code rates 1/2 and 1/3. Reconfiguration of the architecture does not require FPGA reprogramming. With a throughput of 70 Mbps, the proposed decoder is suitable for use in receiver architectures of 802.11a, 802.16, 3G and GSM","PeriodicalId":125310,"journal":{"name":"2006 3rd International Conference on Electrical and Electronics Engineering","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"A Runtime Reconfigurable Architecture for Viterbi Decoding\",\"authors\":\"Juan M. Campos, René Cumplido\",\"doi\":\"10.1109/ICEEE.2006.251908\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design and implementation of a runtime reconfigurable architecture for Viterbi decoding with a high throughput rate suitable for software defined radio (SDR). SDR is a radio that is substantially defined in software and whose physical layer behavior can be significantly altered through changes to its software. The architecture can be reconfigured to decode convolutionally coded data with constraint lengths from 3 to 7 and code rates 1/2 and 1/3. Reconfiguration of the architecture does not require FPGA reprogramming. With a throughput of 70 Mbps, the proposed decoder is suitable for use in receiver architectures of 802.11a, 802.16, 3G and GSM\",\"PeriodicalId\":125310,\"journal\":{\"name\":\"2006 3rd International Conference on Electrical and Electronics Engineering\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-12-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 3rd International Conference on Electrical and Electronics Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEEE.2006.251908\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 3rd International Conference on Electrical and Electronics Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEEE.2006.251908","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Runtime Reconfigurable Architecture for Viterbi Decoding
This paper presents the design and implementation of a runtime reconfigurable architecture for Viterbi decoding with a high throughput rate suitable for software defined radio (SDR). SDR is a radio that is substantially defined in software and whose physical layer behavior can be significantly altered through changes to its software. The architecture can be reconfigured to decode convolutionally coded data with constraint lengths from 3 to 7 and code rates 1/2 and 1/3. Reconfiguration of the architecture does not require FPGA reprogramming. With a throughput of 70 Mbps, the proposed decoder is suitable for use in receiver architectures of 802.11a, 802.16, 3G and GSM
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