具有使能输入的传统解码器逻辑的容错量子实现

IF 1 4区 工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC
Laxmidhar Biswal, Bappaditya Mondal, Hafizur Rahaman
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引用次数: 1

摘要

退相干是物理实现可扩展量子计算机的最大障碍,它危及量子比特的相干叠加,使量子比特极其脆弱。量子纠错码(QECC)和容错量子计算可以共同保护量子比特,提高可扩展性。另一方面,传统的逻辑电路由于与量子逻辑有很大的不同,在量子计算中不再有用。然而,量子计算机必须执行经典任务,这些任务可以通过转换为其等效的量子算法来解决。在此基础上,提出了一种基于零垃圾的可逆容错量子电路,适用于具有Clifford + t群使能信号的1:2和2:4解码器。在此基础上,进一步扩展了基于线性T -深度容错量子逻辑的n: 2n解码器的设计方法。此外,对n: 2n解码器的性能参数如T - count, T - depth和垃圾输出进行了评估。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

Fault-tolerant quantum implementation of conventional decoder logic with enable input

Fault-tolerant quantum implementation of conventional decoder logic with enable input

Decoherence is the greatest obstacle to the physical realization of scalable quantum computer, jeopardises coherent superposition of the qubit, and makes qubit extremely fragile. Quantum Error Correction Code (QECC), and Fault-tolerant quantum computation collectively could protect qubit and improve scalability. On the other hand, the conventional logic circuit is no more useful in quantum computing due to much difference from quantum logic. However, quantum computer has to perform classical tasks which can be addressed by translating to its equivalent quantum algorithm. Herein, zero-garbage-based reversible and fault-tolerant quantum circuit for 1 : 2, and 2 : 4 Decoder with enable signal using Clifford + T-group are proposed. Further, the design approach to implement n : 2n decoder on fault-tolerant quantum logic in linear T − depth is extended. Besides, performance parameters likely T − count, T − depth, and garbage output have been evaluated for n : 2n decoder.

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来源期刊
Iet Circuits Devices & Systems
Iet Circuits Devices & Systems 工程技术-工程:电子与电气
CiteScore
3.80
自引率
7.70%
发文量
32
审稿时长
3 months
期刊介绍: IET Circuits, Devices & Systems covers the following topics: Circuit theory and design, circuit analysis and simulation, computer aided design Filters (analogue and switched capacitor) Circuit implementations, cells and architectures for integration including VLSI Testability, fault tolerant design, minimisation of circuits and CAD for VLSI Novel or improved electronic devices for both traditional and emerging technologies including nanoelectronics and MEMs Device and process characterisation, device parameter extraction schemes Mathematics of circuits and systems theory Test and measurement techniques involving electronic circuits, circuits for industrial applications, sensors and transducers
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