A novel approach for Low Voltage, Low Power deep Sub-threshold 5-T SRAM cell

In this paper, we introduce a new low power & high static noise margin (SNM) deep sub-threshold 5-T SRAM cell which can be operated properly below the threshold value of devices in deep submicron .13μm CMOS technology. The new design is slightly different to 6T SRAM cell [15]. This design achieves an average 36.11% reduction in power dissipation for (1.2–1.8) volt supply voltage and achieves an average 106.60% improvement in static noise margin (SNM) for the same supply voltage. The reduction in power dissipation and improvement of SNM increases when we reduce the supply voltage below the 1.2 volts compared to existing 6T SRAM cell. (i.e. sub-threshold voltage).