{"title":"基于FPGA的数字正弦余弦波发生器的流水线CORDIC设计","authors":"E.I. Garcia, R. Cumplido, M. Arias","doi":"10.1109/ICEEE.2006.251917","DOIUrl":null,"url":null,"abstract":"Sine and cosine waves have been used in countless applications; in recent research on software defined radio (SDR), digital modalities of sine and cosine waves have received special attention. SDR involves highly reconfigurable resources and uses digital generated waves for modulation and demodulation of signals. Coordinate rotation digital computer (CORDIC) is a well known algorithm used to approximate iteratively some transcendental functions. In this work, a pipelined CORDIC architecture is used for designing a flexible and scalable digital sine and cosine waves generator. An FPGA-based architecture is presented and the design has been implemented on a Xilinx Spartan 3 device. Synthesis and implementation results are shown and discussed","PeriodicalId":125310,"journal":{"name":"2006 3rd International Conference on Electrical and Electronics Engineering","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"47","resultStr":"{\"title\":\"Pipelined CORDIC Design on FPGA for a Digital Sine and Cosine Waves Generator\",\"authors\":\"E.I. Garcia, R. Cumplido, M. Arias\",\"doi\":\"10.1109/ICEEE.2006.251917\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Sine and cosine waves have been used in countless applications; in recent research on software defined radio (SDR), digital modalities of sine and cosine waves have received special attention. SDR involves highly reconfigurable resources and uses digital generated waves for modulation and demodulation of signals. Coordinate rotation digital computer (CORDIC) is a well known algorithm used to approximate iteratively some transcendental functions. In this work, a pipelined CORDIC architecture is used for designing a flexible and scalable digital sine and cosine waves generator. An FPGA-based architecture is presented and the design has been implemented on a Xilinx Spartan 3 device. Synthesis and implementation results are shown and discussed\",\"PeriodicalId\":125310,\"journal\":{\"name\":\"2006 3rd International Conference on Electrical and Electronics Engineering\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-12-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"47\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 3rd International Conference on Electrical and Electronics Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEEE.2006.251917\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 3rd International Conference on Electrical and Electronics Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEEE.2006.251917","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Pipelined CORDIC Design on FPGA for a Digital Sine and Cosine Waves Generator
Sine and cosine waves have been used in countless applications; in recent research on software defined radio (SDR), digital modalities of sine and cosine waves have received special attention. SDR involves highly reconfigurable resources and uses digital generated waves for modulation and demodulation of signals. Coordinate rotation digital computer (CORDIC) is a well known algorithm used to approximate iteratively some transcendental functions. In this work, a pipelined CORDIC architecture is used for designing a flexible and scalable digital sine and cosine waves generator. An FPGA-based architecture is presented and the design has been implemented on a Xilinx Spartan 3 device. Synthesis and implementation results are shown and discussed