Using static analysis for coverage extraction fromemulation/prototyping platforms

Full-system emulation and prototyping is now being used widely in the industry for System-on-Chip (SoC) verification. Emulation/ prototyping platforms run tests in a fraction of time compared to the traditional simulation based verification. However, unlike simulation, they do not provide visibility into the hardware design source code. As a result, they fail to provide any information about code coverage achieved, which is an important metric to measure the completeness of the verification process. In this paper, we present a novel technique to extract code coverage from emulation/prototyping platforms. Through analysis of the source code for the hardware design, we relate the evaluation of branch conditions to other statements in the code. Evaluation of the branch conditions is recorded using additional logic during emulation, and mapped back to the code to obtain coverage information. We apply our technique to an industrial system, and show that it can efficiently provide code coverage statistics that are faithful to the coverage obtained from simulation. We also perform experiments on the publicly available OpenRISC processor and demonstrate similar results.