W. Fornaciari, V. Trianni, C. Brandolese, D. Sciuto, F. Salice, G. Beltrame
{"title":"超标量体系结构中的装配指令时序建模","authors":"W. Fornaciari, V. Trianni, C. Brandolese, D. Sciuto, F. Salice, G. Beltrame","doi":"10.1145/581199.581230","DOIUrl":null,"url":null,"abstract":"This paper proposes an original model of the execution time of assembly instructions in superscalar architectures. The approach is based on a rigorous mathematical model and provides a methodology and a toolset to perform data analysis and model tuning. The methodology also provides a framework for building new trace simulators for generic architectures. The results obtained show a good accuracy paired with a satisfactory computational efficiency.","PeriodicalId":413693,"journal":{"name":"15th International Symposium on System Synthesis, 2002.","volume":"519 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Modeling assembly instruction timing in superscalar architectures\",\"authors\":\"W. Fornaciari, V. Trianni, C. Brandolese, D. Sciuto, F. Salice, G. Beltrame\",\"doi\":\"10.1145/581199.581230\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes an original model of the execution time of assembly instructions in superscalar architectures. The approach is based on a rigorous mathematical model and provides a methodology and a toolset to perform data analysis and model tuning. The methodology also provides a framework for building new trace simulators for generic architectures. The results obtained show a good accuracy paired with a satisfactory computational efficiency.\",\"PeriodicalId\":413693,\"journal\":{\"name\":\"15th International Symposium on System Synthesis, 2002.\",\"volume\":\"519 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-10-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"15th International Symposium on System Synthesis, 2002.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/581199.581230\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"15th International Symposium on System Synthesis, 2002.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/581199.581230","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Modeling assembly instruction timing in superscalar architectures
This paper proposes an original model of the execution time of assembly instructions in superscalar architectures. The approach is based on a rigorous mathematical model and provides a methodology and a toolset to perform data analysis and model tuning. The methodology also provides a framework for building new trace simulators for generic architectures. The results obtained show a good accuracy paired with a satisfactory computational efficiency.