在裸片级筛选ic:临时封装

Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1992-09-28 DOI:10.1109/IEMT.1992.639895

D. Chu, C. Reber, D. Palmer

{"title":"在裸片级筛选ic:临时封装","authors":"D. Chu, C. Reber, D. Palmer","doi":"10.1109/IEMT.1992.639895","DOIUrl":null,"url":null,"abstract":"Several different temporary packaging concepts for integrated circuits (ICs) for pretest at speed and burn-in are introduced. Temporary packaging is achieved using standard labor and equipment resources already employed in permanent packaging. Experiments were carried out to validate the pretest process, and results are presented for the various materials used in the pretest process. The preferred method for temporary packaging along with the selected materials used is presented. Temporary packaging of integrated circuits for pretest with reasonable yield is demonstrated as feasible. >","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Screening ICs On The Bare Chip Level: Temporary Packaging\",\"authors\":\"D. Chu, C. Reber, D. Palmer\",\"doi\":\"10.1109/IEMT.1992.639895\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Several different temporary packaging concepts for integrated circuits (ICs) for pretest at speed and burn-in are introduced. Temporary packaging is achieved using standard labor and equipment resources already employed in permanent packaging. Experiments were carried out to validate the pretest process, and results are presented for the various materials used in the pretest process. The preferred method for temporary packaging along with the selected materials used is presented. Temporary packaging of integrated circuits for pretest with reasonable yield is demonstrated as feasible. >\",\"PeriodicalId\":403090,\"journal\":{\"name\":\"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-09-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEMT.1992.639895\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEMT.1992.639895","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

介绍了几种不同的集成电路(ic)的临时封装概念，用于速度预测试和老化。临时包装是使用标准的劳动力和设备资源，已经在永久包装中使用。实验验证了预试过程，并给出了预试过程中使用的各种材料的结果。提出了临时包装的优选方法以及所选用的材料。以合理的成品率证明了集成电路临时封装预测的可行性。>

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Screening ICs On The Bare Chip Level: Temporary Packaging

Several different temporary packaging concepts for integrated circuits (ICs) for pretest at speed and burn-in are introduced. Temporary packaging is achieved using standard labor and equipment resources already employed in permanent packaging. Experiments were carried out to validate the pretest process, and results are presented for the various materials used in the pretest process. The preferred method for temporary packaging along with the selected materials used is presented. Temporary packaging of integrated circuits for pretest with reasonable yield is demonstrated as feasible. >

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium

自引率

0.00%

发文量