Organic transistor technology options for device performance versus technology options for increased circuit reliability and yield on foil

Last year, advances in organic device technology (such as device scaling, high K-dielectrics [1], … ) enabled a substantial progress in performance. This resulted in an increase in the data rate of plastic transponder circuits from about 2 kbit/s [2] to EPC-compatible speeds (50 kbit/s). The organic semiconductor pentacene deposited from solution was replaced by a better-performing vapor-phase deposited pentacene, with a mobility being a factor of 3 higher. The isolation of pentacene transistors in this new process is achieved by an integrated shadow mask, shown in Fig. 1, that results in a reliable isolation of the semiconductor area testified by off-currents below 10pA. We replaced the organic polymer (low-k) dielectric with a 100-nm thick high-k dielectric, sputtered Al2O3, resulting in an 8-fold higher specific accumulation capacitance. That, in turn, allowed for downscaling the transistor channel length from 5µm to 2µm, while maintaining a high output resistance in saturation - and therefore also high inverter gain and noise margins. A cross-section of this process flow is depicted in Fig. 1. Fig. 2 shows a micrograph image of a 5-stage ring oscillator realized in this technology on foil optimized for speed. This organic thin-film circuit technology allows to design with lower overlap capacitance and to downscale the transistor channel length, within the boundaries achievable by existing high-throughput manufacturing tools (e.g. steppers used in backplane manufacturing). In this work, we varied the channel lengths (L) of the TFTs in the circuits between 20µm and 2µm and limited the gate-source and gate-drain overlap capacitances by decreasing the width of the finger-shaped source and drain contacts, that fully overlap the gate, from 5µm to 2µm. Fig. 2 shows a micrograph image of one transistor. Typical transfer curves of transistors fabricated in this technology, having L = 5µm and 2µm, are depicted in Fig. 3 and Fig. 4 respectively. The transistors are normally-on and their charge carrier (hole) mobility exceeds 0.5cm2/Vs. Fig. 5 shows typical transfer curves of a zerovgs-load inverters with channel lengths of 5µm and 2µm. The ratio between drive and load transistor is 10∶1. The inverters have high gains and noise margins. The stage delay (τD) of inverters in this technology is plotted as a function of the supply voltage in Fig. 6. The stage delay is determined from 19-stage ring oscillators. The figure shows τD for inverters with channel lengths from 20µm to 2µm and gate-overlap of the transistor-fingers ranging from 5µm to 2µm. Stage delays below 1µs, and as low as 400ns, are shown at VDD=10V. To our knowledge, no plastic technology was shown before with such speeds at these low power voltages. The effect of decreasing the overlap capacitance is also shown for the two smaller channel lengths: shrinking the overlap from 5µm to 2µm improves the stage delay by a factor of 1.5 to 2. We proceeded with the design and realization of 8bit organic RFID transponder chips, having a channel length of 2µm and either 5µm or 2µm finger widths. Figs. 7 and 8 show the photographs of the 6″ wafer and a zoom of the die, Fig. 9 shows the corresponding schematic. Fig. 11 depicts the output signal of both types of transponders. In agreement with the two-fold faster inverter stage delay for the 2µm fingers, the data rate of this transponder is also twice as high as that of the design with 5µm fingers. The obtained data rate of the 8bit transponder with channel length and fingers of 2µm is a record 50kb/s.