RF-CMOS性能趋势

P. Woerlee, M. J. Knitel, R. V. Langevelde, D. Klaassen, L. Tiemeijer, A. Scholten, A. Z. Duijnhoven
{"title":"RF-CMOS性能趋势","authors":"P. Woerlee, M. J. Knitel, R. V. Langevelde, D. Klaassen, L. Tiemeijer, A. Scholten, A. Z. Duijnhoven","doi":"10.1109/ESSDERC.2000.194843","DOIUrl":null,"url":null,"abstract":"The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices from 350-nm to 50-nm CMOS technologies are presented. Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used to evaluate the RF performance. RF performance metrics such as the cutoff frequency, maximum oscillation frequency, power gain, noise figure, linearity, and 1 noise were included in the analysis. The focus of the study was on gate and drain bias conditions relevant for RF circuit design. A scaling methodology for RF-CMOS based on limited linearity degradation is proposed.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"332","resultStr":"{\"title\":\"RF-CMOS Performance Trends\",\"authors\":\"P. Woerlee, M. J. Knitel, R. V. Langevelde, D. Klaassen, L. Tiemeijer, A. Scholten, A. Z. Duijnhoven\",\"doi\":\"10.1109/ESSDERC.2000.194843\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices from 350-nm to 50-nm CMOS technologies are presented. Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used to evaluate the RF performance. RF performance metrics such as the cutoff frequency, maximum oscillation frequency, power gain, noise figure, linearity, and 1 noise were included in the analysis. The focus of the study was on gate and drain bias conditions relevant for RF circuit design. A scaling methodology for RF-CMOS based on limited linearity degradation is proposed.\",\"PeriodicalId\":354721,\"journal\":{\"name\":\"30th European Solid-State Device Research Conference\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-09-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"332\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"30th European Solid-State Device Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.2000.194843\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"30th European Solid-State Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2000.194843","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 332

摘要

研究了缩放对MOS器件在射频频率下模拟性能的影响。从350纳米到50纳米的CMOS技术,提出了标称栅长NMOS器件射频性能的趋势。实验数据和电路模拟与先进的验证紧凑模型(MOS模型11)被用来评估射频性能。RF性能指标包括截止频率、最大振荡频率、功率增益、噪声系数、线性度和1噪声。研究的重点是与射频电路设计相关的栅极和漏极偏置条件。提出了一种基于有限线性退化的RF-CMOS标度方法。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
RF-CMOS Performance Trends
The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices from 350-nm to 50-nm CMOS technologies are presented. Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used to evaluate the RF performance. RF performance metrics such as the cutoff frequency, maximum oscillation frequency, power gain, noise figure, linearity, and 1 noise were included in the analysis. The focus of the study was on gate and drain bias conditions relevant for RF circuit design. A scaling methodology for RF-CMOS based on limited linearity degradation is proposed.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信