High-performance dynamic circuit techniques with improved noise immunity for address decoders

Dynamic circuits are extensively employed in very-large-scale integration chips because of their high performance. Unfortunately, they are more susceptible to noise than static complementary metal oxide semiconductor circuits. With the continuous down-scaling of process technology and the supply voltage, improved noise immunity in dynamic circuits is essential. In this study, two new schemes are proposed to enhance the noise tolerance of dynamic address decoders, and their performance, noise tolerance and power consumption are compared with those of a conventional dynamic decoding circuit and a previous scheme. A dynamic 4–16 decoder employing the proposed delay technique exhibits 131.5 and 2.6% improvements in noise tolerance and performance, respectively, whereas a 4–16 decoder exploiting the proposed mirror scheme achieves 291.2 and 25.2% improvements; both used 65 nm process technology. Moreover, the proposed techniques are more resistant to process variations and more tolerant of a lower power supply.