{"title":"Z-RAM®90nm及以下超致密内存","authors":"D. Fisch, Anant Singh, Greg Popov","doi":"10.1109/HOTCHIPS.2006.7477748","DOIUrl":null,"url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation on Innovative Silicon's Z-RAM, an ultra-dense memory processor. Some of the specific topics discussed include: an overview of the device and its system architecture; major processing challenges; and key Z-RAM performance factors, including memory density, speed processing, pipeline operations, routing impact, active power capabilities, and standby power facilities.","PeriodicalId":302249,"journal":{"name":"2006 IEEE Hot Chips 18 Symposium (HCS)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Z-RAM® ultra-dense memory for 90nm and below\",\"authors\":\"D. Fisch, Anant Singh, Greg Popov\",\"doi\":\"10.1109/HOTCHIPS.2006.7477748\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article consists of a collection of slides from the author's conference presentation on Innovative Silicon's Z-RAM, an ultra-dense memory processor. Some of the specific topics discussed include: an overview of the device and its system architecture; major processing challenges; and key Z-RAM performance factors, including memory density, speed processing, pipeline operations, routing impact, active power capabilities, and standby power facilities.\",\"PeriodicalId\":302249,\"journal\":{\"name\":\"2006 IEEE Hot Chips 18 Symposium (HCS)\",\"volume\":\"102 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE Hot Chips 18 Symposium (HCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HOTCHIPS.2006.7477748\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Hot Chips 18 Symposium (HCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HOTCHIPS.2006.7477748","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This article consists of a collection of slides from the author's conference presentation on Innovative Silicon's Z-RAM, an ultra-dense memory processor. Some of the specific topics discussed include: an overview of the device and its system architecture; major processing challenges; and key Z-RAM performance factors, including memory density, speed processing, pipeline operations, routing impact, active power capabilities, and standby power facilities.