Modelling and Simulation of 10nm Strained Channel DG- Nano-FET

Strained silicon technology is one of the promising technology for sub-10nm Metal Oxide Semiconductor Field Effect Transistor (MOSFET) design. To match with advance technology node device dimension have to reduce which leads to several short channel effects. By using strain silicon technology DG-Nano-FET is developed at 10nm gate length providing a promising substitute in order to restrict performance degradation beyond 14nm channel length. The newly designed double gate (DG)-Nano-FET modeled here comprises of the three layer system as s-Si/s-SiGe/s-Si in channel region with lightly doped channel, which result in mobility enhancement in channel region. Due to additional control with two gates in the device the charge carriers flows from source to drain experiencing quantum carrier confinement in the narrow channel. The strained channel DG-Nano-FET developed on 10nm channel length have 57.5% enrichment in drain current as comparison to 22nm DG – SHOI FET.