20ns 64K CMOS SRAM

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1984.1156700

O. Minato, T. Masuhara, T. Sasaki, Y. Sakai, T. Hayashida

{"title":"20ns 64K CMOS SRAM","authors":"O. Minato, T. Masuhara, T. Sasaki, Y. Sakai, T. Hayashida","doi":"10.1109/ISSCC.1984.1156700","DOIUrl":null,"url":null,"abstract":"A 19.0mm264K×1 SRAM utilizing pulsed-word-line technique, P-well/bipolar technology, and 1.3μm gate MOS transistors, will be described. The RAM has typical address access time of 20ns and power dissipation of 70mW at 1 MHz cycle time.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"34","resultStr":"{\"title\":\"A 20ns 64K CMOS SRAM\",\"authors\":\"O. Minato, T. Masuhara, T. Sasaki, Y. Sakai, T. Hayashida\",\"doi\":\"10.1109/ISSCC.1984.1156700\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 19.0mm264K×1 SRAM utilizing pulsed-word-line technique, P-well/bipolar technology, and 1.3μm gate MOS transistors, will be described. The RAM has typical address access time of 20ns and power dissipation of 70mW at 1 MHz cycle time.\",\"PeriodicalId\":260117,\"journal\":{\"name\":\"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"34\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1984.1156700\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1984.1156700","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 34

摘要

将介绍利用脉冲字线技术、p阱/双极技术和1.3μm栅极MOS晶体管的19.0mm264K×1 SRAM。该RAM的典型地址访问时间为20ns，在1mhz周期时间下功耗为70mW。

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A 20ns 64K CMOS SRAM

A 19.0mm264K×1 SRAM utilizing pulsed-word-line technique, P-well/bipolar technology, and 1.3μm gate MOS transistors, will be described. The RAM has typical address access time of 20ns and power dissipation of 70mW at 1 MHz cycle time.

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来源期刊

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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