Yan Li, Yu Hang, Lai Jiang, Zhen Ji, Jun Zhu, M. Niu, P. Xiao
{"title":"一种用于正电子发射断层扫描多电压阈值法的CMOS时数转换器","authors":"Yan Li, Yu Hang, Lai Jiang, Zhen Ji, Jun Zhu, M. Niu, P. Xiao","doi":"10.1109/EDSSC.2013.6628151","DOIUrl":null,"url":null,"abstract":"Avoiding use of traditional high-speed analog-to digital converters (ADCs) and constant fraction discriminators, multi-voltage threshold (MVT) method is able to digitally sample positron emission tomography (PET) scintillation pulse with reasonable cost. As the key component of the MVT method, a time-to-digital convertor (TDC) with high resolution and large dynamic range is presented in this work. The TDC architecture uses a delay locked loop (DLL) to generate the fast clock edges from a 100 MHz clock, and a 32-stage Vernier delay lines (VDL) is used to achieve the 40pS timing resolution. The proposed TDC is designed using the standard 0.25 μm CMOS technology with 2.5V normal supply voltage. The power consumption of the TDC is ~70 mW.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A CMOS time-to-digital converter for multi-voltage threshold method in positron emission tomography\",\"authors\":\"Yan Li, Yu Hang, Lai Jiang, Zhen Ji, Jun Zhu, M. Niu, P. Xiao\",\"doi\":\"10.1109/EDSSC.2013.6628151\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Avoiding use of traditional high-speed analog-to digital converters (ADCs) and constant fraction discriminators, multi-voltage threshold (MVT) method is able to digitally sample positron emission tomography (PET) scintillation pulse with reasonable cost. As the key component of the MVT method, a time-to-digital convertor (TDC) with high resolution and large dynamic range is presented in this work. The TDC architecture uses a delay locked loop (DLL) to generate the fast clock edges from a 100 MHz clock, and a 32-stage Vernier delay lines (VDL) is used to achieve the 40pS timing resolution. The proposed TDC is designed using the standard 0.25 μm CMOS technology with 2.5V normal supply voltage. The power consumption of the TDC is ~70 mW.\",\"PeriodicalId\":333267,\"journal\":{\"name\":\"2013 IEEE International Conference of Electron Devices and Solid-state Circuits\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-06-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE International Conference of Electron Devices and Solid-state Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDSSC.2013.6628151\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2013.6628151","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A CMOS time-to-digital converter for multi-voltage threshold method in positron emission tomography
Avoiding use of traditional high-speed analog-to digital converters (ADCs) and constant fraction discriminators, multi-voltage threshold (MVT) method is able to digitally sample positron emission tomography (PET) scintillation pulse with reasonable cost. As the key component of the MVT method, a time-to-digital convertor (TDC) with high resolution and large dynamic range is presented in this work. The TDC architecture uses a delay locked loop (DLL) to generate the fast clock edges from a 100 MHz clock, and a 32-stage Vernier delay lines (VDL) is used to achieve the 40pS timing resolution. The proposed TDC is designed using the standard 0.25 μm CMOS technology with 2.5V normal supply voltage. The power consumption of the TDC is ~70 mW.