正交直接数字下变频器

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI:10.1109/CICC.2002.1012803

P. Vancorenland, P. Coppejans, W. D. Cock, M. Steyaert

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引用次数: 3

摘要

提出了一种正交直接数字下变频(DDD)。转换器具有一个连续的时间/spl δ //spl σ /噪声整形环滤波器，具有正交带通特性。通过在AD转换器中集成混频器，可以将0.3-1.6 GHz范围内的射频输入信号以128 MHz的比特率下变频为数字I和Q输出流。该电路被设计为低功率接收器的前端，具有以4 MHz为中心的2 MHz宽中频带宽。转换器集成在0.25 /spl μ m CMOS技术中，从2v电源消耗14mw。

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A quadrature direct digital downconverter

A quadrature direct digital down converter (DDD) is presented. The converter has a continuous time /spl Delta//spl Sigma/ noise shaping loopfilter with a quadrature bandpass characteristic. Through the integration of mixers in the AD converter, RF input signals in the range 0.3-1.6 GHz can be downconverted to a digital I and Q output stream at a bit rate of 128 MHz. The circuit is designed as a front-end for low power receivers with a 2 MHz wide IF bandwidth centered around 4 MHz. The converter, integrated in a 0.25 /spl mu/m CMOS technology, consumes 14 mW from a 2 V supply.

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Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)

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