{"title":"蔡氏电路边界面的并行计算","authors":"Z. Rácz, B. Sobota, M. Guzan","doi":"10.1109/RADIOELEK.2017.7937582","DOIUrl":null,"url":null,"abstract":"This paper introduces a method for performing parallel computations of the boundary surface of Chua's circuit. The presented approach could be characterized as a SIMD method which is based on the utilization of all available CPU cores. Performance comparisons between single and parallelized calculations on different computer systems are included in a table at the end of the article. The best results were observed using the highest compiler optimisation options on 64 bit architecture and using Intel i7 CPUs.","PeriodicalId":160577,"journal":{"name":"2017 27th International Conference Radioelektronika (RADIOELEKTRONIKA)","volume":"344 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Parallelizing boundary surface computation of Chua's circuit\",\"authors\":\"Z. Rácz, B. Sobota, M. Guzan\",\"doi\":\"10.1109/RADIOELEK.2017.7937582\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper introduces a method for performing parallel computations of the boundary surface of Chua's circuit. The presented approach could be characterized as a SIMD method which is based on the utilization of all available CPU cores. Performance comparisons between single and parallelized calculations on different computer systems are included in a table at the end of the article. The best results were observed using the highest compiler optimisation options on 64 bit architecture and using Intel i7 CPUs.\",\"PeriodicalId\":160577,\"journal\":{\"name\":\"2017 27th International Conference Radioelektronika (RADIOELEKTRONIKA)\",\"volume\":\"344 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 27th International Conference Radioelektronika (RADIOELEKTRONIKA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RADIOELEK.2017.7937582\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 27th International Conference Radioelektronika (RADIOELEKTRONIKA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RADIOELEK.2017.7937582","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Parallelizing boundary surface computation of Chua's circuit
This paper introduces a method for performing parallel computations of the boundary surface of Chua's circuit. The presented approach could be characterized as a SIMD method which is based on the utilization of all available CPU cores. Performance comparisons between single and parallelized calculations on different computer systems are included in a table at the end of the article. The best results were observed using the highest compiler optimisation options on 64 bit architecture and using Intel i7 CPUs.
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