256k nmos DRAM

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1984.1156712

E. Baier, R. Clemen, W. Haug, W. Fischer, R. Mueller, W. Loehlein, H. Barsuhn

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引用次数: 3

摘要

本文将讨论一种80ns 256K n通道金属门DRAM，该DRAM具有可选的数据I/O缓冲器，允许芯片用作64K×4、128 × 2或256 × 1，并以20ns数据速率进行并行或串行数据传输。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 256K NMOS DRAM

A 80ns 256K n-channel metal-gate DRAM with tour selectable data I/O buffers which permit the chip to be used as 64K×4, 128 × 2, or 256 × 1, with either parallel or serial data transfer at 20ns data rate, will be discussed.

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来源期刊

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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