基于TSV 2.5D封装的仿真芯片设计

Gao Nayan, Cao Yuyuan, Zhu Yuan, Ming Xue-fei
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引用次数: 1

摘要

随着微电子技术的发展,微电子封装已经从传统的二维封装发展到高密度、多芯片的三维封装。因此,2.5D或3D封装发展迅速。2.5D封装与3d封装相比结构简单,易于在短时间内应用于产品中。因此,2.5D封装已成为一种流行的方式,使封装小,轻,多功能。本文重点研究了一种基于2.5D封装的仿真芯片设计方法。由于一直在研究的Virtex-7的结构,有必要设计一个仿真芯片用于验证2.5D封装的封装技术。这种方法有利于缩短设计周期,节约生产成本。此外,它有利于深入研究2.5D封装。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Imitation chip design based on TSV 2.5D package
With the development of microelectronics technology, the microelectronic package has been developed from traditional 2D package to 3D package which is high-density and multi-chip. Therefore 2.5D or 3D package has developed rapidly. The structure of 2.5D package is simply compared with 3Dpackage, so it is easy to apply in products in a short time. As a result, 2.5D package has become a popular way to make the package small, light and multi-functional. This paper focuses on a method to design imitation chip based on 2.5D package. Due to the structure of Virtex-7 which has been researching, it is necessary to design an imitation chip to apply in verifying the encapsulation technology of 2.5D package. This method is beneficial to shorten the design period and save the cost of production. Furthermore, it is in favor of studying 2.5D package deeply.
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