{"title":"基于每个方向圆形缓冲单元的新型FPGA加速器,用于快速优化GLCM和纹理特征计算","authors":"Mohamed Amin Ben Atitallah, R. Kachouri, H. Mnif","doi":"10.1109/DTSS.2019.8915341","DOIUrl":null,"url":null,"abstract":"This paper presents an FPGA accelerator based on circular buffer unit per orientation for a fast and optimized Gray Level Co-occurrence Matrix (GLCM) and four Texture features computation. The Four texture features namely, contrast, energy, dissimilarity and correlation are computed using Xilinx FPGA. However, the computation of GLCM and four textures features are very complex and consume a lot of execution time. In this paper, an FPGA accelerator for fast computation of GLCM and four texture features are designed and implemented. This architecture was implemented on a Xilinx Zc-702 using Vivado HLS. The obtained results are then compared against other related works. The synthesis results on FPGA prove a significant gain (about 17%) in execution time compared to the previous work.","PeriodicalId":342516,"journal":{"name":"2019 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A new FPGA Accelerator Based on Circular Buffer Unit Per Orientation for a Fast and Optimised GLCM and Texture Feature Computation\",\"authors\":\"Mohamed Amin Ben Atitallah, R. Kachouri, H. Mnif\",\"doi\":\"10.1109/DTSS.2019.8915341\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an FPGA accelerator based on circular buffer unit per orientation for a fast and optimized Gray Level Co-occurrence Matrix (GLCM) and four Texture features computation. The Four texture features namely, contrast, energy, dissimilarity and correlation are computed using Xilinx FPGA. However, the computation of GLCM and four textures features are very complex and consume a lot of execution time. In this paper, an FPGA accelerator for fast computation of GLCM and four texture features are designed and implemented. This architecture was implemented on a Xilinx Zc-702 using Vivado HLS. The obtained results are then compared against other related works. The synthesis results on FPGA prove a significant gain (about 17%) in execution time compared to the previous work.\",\"PeriodicalId\":342516,\"journal\":{\"name\":\"2019 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DTSS.2019.8915341\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DTSS.2019.8915341","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new FPGA Accelerator Based on Circular Buffer Unit Per Orientation for a Fast and Optimised GLCM and Texture Feature Computation
This paper presents an FPGA accelerator based on circular buffer unit per orientation for a fast and optimized Gray Level Co-occurrence Matrix (GLCM) and four Texture features computation. The Four texture features namely, contrast, energy, dissimilarity and correlation are computed using Xilinx FPGA. However, the computation of GLCM and four textures features are very complex and consume a lot of execution time. In this paper, an FPGA accelerator for fast computation of GLCM and four texture features are designed and implemented. This architecture was implemented on a Xilinx Zc-702 using Vivado HLS. The obtained results are then compared against other related works. The synthesis results on FPGA prove a significant gain (about 17%) in execution time compared to the previous work.