{"title":"一种精度为5mv的FLASH多级存储自适应编程方法","authors":"L. Engh, A. Kordesch, C. Mai-Liu","doi":"10.1109/CICC.2002.1012779","DOIUrl":null,"url":null,"abstract":"The presented multi-level storage memory system uses a self-adaptive method that improves the cell model with each successive program cycle, and accommodates cell variations and noise. An accuracy of 5 mV is achieved within eight cycles, which total 125 /spl mu/s. Algorithm control circuits occupy 1 mm/sup 2/ of area in a 0.5 /spl mu/m SSI FLASH process.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A self adaptive programming method with 5 mV accuracy for multi-level storage in FLASH\",\"authors\":\"L. Engh, A. Kordesch, C. Mai-Liu\",\"doi\":\"10.1109/CICC.2002.1012779\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The presented multi-level storage memory system uses a self-adaptive method that improves the cell model with each successive program cycle, and accommodates cell variations and noise. An accuracy of 5 mV is achieved within eight cycles, which total 125 /spl mu/s. Algorithm control circuits occupy 1 mm/sup 2/ of area in a 0.5 /spl mu/m SSI FLASH process.\",\"PeriodicalId\":209025,\"journal\":{\"name\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"volume\":\"97 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2002.1012779\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2002.1012779","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A self adaptive programming method with 5 mV accuracy for multi-level storage in FLASH
The presented multi-level storage memory system uses a self-adaptive method that improves the cell model with each successive program cycle, and accommodates cell variations and noise. An accuracy of 5 mV is achieved within eight cycles, which total 125 /spl mu/s. Algorithm control circuits occupy 1 mm/sup 2/ of area in a 0.5 /spl mu/m SSI FLASH process.