Amit Bhattacharyya, Madhusree Banerjee, Papiya Debnath, D. De, M. Chanda
{"title":"静电掺杂双口袋垂直隧道场效应晶体管的射频/模拟性能分析","authors":"Amit Bhattacharyya, Madhusree Banerjee, Papiya Debnath, D. De, M. Chanda","doi":"10.1109/VLSIDCS53788.2022.9811496","DOIUrl":null,"url":null,"abstract":"Reduction of ambipolar characteristics, including enhanced Analog and RF figure of merits (FoMs) has been proposed by utilizing a charge plasma (CP) based doping less (DL) tunnel FET (TFET) configuration. In addition, the doping less configuration affords easiness in fabrication as well as protection next to random dopant fluctuations (RDFs) in contrast through the traditionally doped Tunnel-FET. Now, by introducing tunneling metallic plate (TMP) double (top and bottom) pockets of n+ type have been structured merely adjacent to source and channel interface. An evaluation of the presentations of recommended electrostatically doping double pocket vertically TFET (ED-DP-V-TFET) arrangement with usual lateral (L) and solitary pocket (SP) TFETs have been executed regarding device features. The suggested representation proposes advanced appearance than other TFET contestant. Furthermore, the proposed form is examined for Analog and RF FoMs through the deviation of work-function (WF) of TE and dielectric thickness (Tox) beneath TE with SILVACO ATLAS simulator. Efficiency of the suggested configuration in Analog and RF realm has been validated by the simulated outcomes.","PeriodicalId":307414,"journal":{"name":"2022 IEEE VLSI Device Circuit and System (VLSI DCS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-02-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"RF/Analog Performance Analysis of Electrostatically Doped Dual Pocket Vertical Tunnel Field Effect Transistor\",\"authors\":\"Amit Bhattacharyya, Madhusree Banerjee, Papiya Debnath, D. De, M. Chanda\",\"doi\":\"10.1109/VLSIDCS53788.2022.9811496\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Reduction of ambipolar characteristics, including enhanced Analog and RF figure of merits (FoMs) has been proposed by utilizing a charge plasma (CP) based doping less (DL) tunnel FET (TFET) configuration. In addition, the doping less configuration affords easiness in fabrication as well as protection next to random dopant fluctuations (RDFs) in contrast through the traditionally doped Tunnel-FET. Now, by introducing tunneling metallic plate (TMP) double (top and bottom) pockets of n+ type have been structured merely adjacent to source and channel interface. An evaluation of the presentations of recommended electrostatically doping double pocket vertically TFET (ED-DP-V-TFET) arrangement with usual lateral (L) and solitary pocket (SP) TFETs have been executed regarding device features. The suggested representation proposes advanced appearance than other TFET contestant. Furthermore, the proposed form is examined for Analog and RF FoMs through the deviation of work-function (WF) of TE and dielectric thickness (Tox) beneath TE with SILVACO ATLAS simulator. Efficiency of the suggested configuration in Analog and RF realm has been validated by the simulated outcomes.\",\"PeriodicalId\":307414,\"journal\":{\"name\":\"2022 IEEE VLSI Device Circuit and System (VLSI DCS)\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-02-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE VLSI Device Circuit and System (VLSI DCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIDCS53788.2022.9811496\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE VLSI Device Circuit and System (VLSI DCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIDCS53788.2022.9811496","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
RF/Analog Performance Analysis of Electrostatically Doped Dual Pocket Vertical Tunnel Field Effect Transistor
Reduction of ambipolar characteristics, including enhanced Analog and RF figure of merits (FoMs) has been proposed by utilizing a charge plasma (CP) based doping less (DL) tunnel FET (TFET) configuration. In addition, the doping less configuration affords easiness in fabrication as well as protection next to random dopant fluctuations (RDFs) in contrast through the traditionally doped Tunnel-FET. Now, by introducing tunneling metallic plate (TMP) double (top and bottom) pockets of n+ type have been structured merely adjacent to source and channel interface. An evaluation of the presentations of recommended electrostatically doping double pocket vertically TFET (ED-DP-V-TFET) arrangement with usual lateral (L) and solitary pocket (SP) TFETs have been executed regarding device features. The suggested representation proposes advanced appearance than other TFET contestant. Furthermore, the proposed form is examined for Analog and RF FoMs through the deviation of work-function (WF) of TE and dielectric thickness (Tox) beneath TE with SILVACO ATLAS simulator. Efficiency of the suggested configuration in Analog and RF realm has been validated by the simulated outcomes.